As the gate length of the MOSFET is scaled down into the sub-50 nm regime for improved performance and density, the requirements for body-doping concentration, gate oxide thickness, and source/drain (S/D) doping profiles to control short-channel effects become increasingly difficult to meet when conventional device structures based on bulk silicon (Si) substrates are employed. The heavy channel doping required to provide adequate suppression of short-channel effects results in degraded mobility and enhanced junction leakage. The aggressive reduction of the silicon dioxide SiO2 gate dielectric thickness for reduced short-channel effects and improved drive current leads to increased direct tunneling gate leakage current and standby power consumption, and also raises concerns regarding the gate oxide reliability. For device scaling well into the sub-50 nm regime, a promising approach to controlling short-channel effects is to use an alternative device structure with multiple-gates, such as the double-gate and the surround-gate or wrap-around gate structure.
A simple example of a multiple-gate device is the double-gate MOSFET structure, where there are two gate electrodes on the opposing sides of the channel. There are several ways in which a double-gate structure can be implemented. One way is the vertical-channel double-gate MOSFET. This is described by U.S. Pat. No. 6,372,559 B1 issued to Crowder et al. for a method of fabricating a self-aligned vertical double-gate MOSFET, and by U.S. Pat. No. 6,406,962 B1 issued to Agnello et al. for a vertical trench-formed dual-gate FET device structure and method for fabrication. A common feature of these two methods is that the source-to-drain direction is oriented normal to the plane of the substrate surface, and the gate-to-gate direction is parallel to the plane of the substrate surface. The device fabrication processes for such a double-gate structure are typically complicated, costly and suffer from poor manufacturability.
Another method to fabricate a double-gate MOSFET is described by U.S. Pat. No. 6,413,802 B1 issued to Hu et al. for fin FET transistor structures having a double gate channel extending vertically from a substrate and methods for manufacture. In U.S. Pat. No. 6,413,802 B1, the device channel comprises a thin silicon fin formed on an insulative substrate (e.g., silicon oxide) and defined using an etchant mask. Gate oxidation is performed, followed by gate deposition and gate patterning to form a double-gate structure overlying the sides of the fin. Both the source-to-drain direction and the gate-to-gate direction are in the plane of the substrate surface. This device structure is widely recognized to be one of the most manufacturable double-gate structures. An integral feature of the double-gate MOSFET described in U.S. Pat. No. 6,413,802 B1 is the etchant mask on the silicon fin. The retention of the etchant mask is crucial due to problems faced in the etch process, particularly relating to the etch selectivity of the gate electrode with respect to the gate dielectric during the gate patterning step.
It is therefore an object of the present invention to provide a multiple-gate transistor structure and a method for fabricating the structure that allows transistor scaling beyond the limits of the conventional bulk silicon MOSFET.